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		VLSI * Microprocessors A Guide to High-Performance Microprocessor Resources
	* VLSI stands for Very Large-Scale Integration

What's new in the VLSI Microprocessors

What's new in  Sun AlphaServer  HP MIPS IBM Motorola QED TI ST Intel AMD Cyrix WinChip Fujitsu NEC Samsung Toshiba

Inside the VLSI Microprocessors Site

Sun Microsystems Microprocessors

	What's new in	Sun Microelectronics	UltraSPARC Family

Very short...

UltraSPARC-III .18 micron 64-bit RISC microprocessor

UltaSPARC-III based systems are available since 27 Sep 2000. UltaSPARC-III is completely new design. It is is focused on scalability, and is able to scale to several hundreds processors in a single system. Embedded DRAM controller eases contention between processors for access to memory. A switch controls the path of data over the system bus between the CPU and memory and can concentrate data flows into a wide stream at relatively high data rates. Operating frequencies are 600 and 750 MHz, performance is 395 SPECint2000 and 421 SPECfp2000 @ 750 MHz 8 MB cache. Contains about 29,000,000 transistors, power dissipation is about 70 Watts. 900MHz version of UltraSPARC-III is in sample production now. Shipments are expected to begin in Dec 2000. Its performance is 467 SPECint2000 and 482 SPECfp2000 An information on the UltraSPARC-III could also be found at UltraSPARC-III home-page from Sun

The UltraSPARC-II is a high-performance, highly-integrated superscalar processor implementing the SPARC-V9 architecture. It is capable of sustaining the execution of up-to four instructions per cycle even in the presence of conditional branches and cache misses. The UltraSPARC-II supports both 2D and 3D graphics as well as image processing, video compression and decompression, and video effects through the VIS Instruction Set. VIS provides high levels of multimedia performance, including real-time H.261 video compression/decompression and a single stream of MPEG-2 decompression at full broadcast quality with no additional hardware support.
The target operating frequencies are 250, 300, 336, 360, 400, 450 and 480MHz, Performance results are 234 SPECint2000, 291 SPECfp2000 (18.3 SPECint95, 30.1 SPECfp95) @ 400 MHz 8 MB L2 cache .

The UltraSPARC i-Series provide a single-chip system solution incorporating a CPU, PCI bus interface, and memory controller. Contains 0.25 to 2 MB L2 cache. The target operating frequencies are 270, 300, 333, 360 and 440 MHz, performance is 18.1 SPECint95, 22.7 SPECfp95 @ 440 MHz 2 MB cache.

The UltraSPARC-I is a high-performance, highly-integrated superscalar processor implementing the SPARC v9 64-bit RISC architecture. The UltraSPARC-I supports 2D, 3D graphics, image processing, video compression and decompression and video effects through the VISual Instruction Set. The target operating frequencies are 143, 167 and 200 MHz, performance is 7.72 SPECint95, 11.4 SPECfp95 @ 200 MHz 1 MB cache.

Suited for low-cost uniprocessor applications. Includes PCI Controller and PCI Bus Interface on chip. Built with the core operating at a low voltage of 3.3V for optimized power consumption. The target operating frequency range is 100-125MHz, performance is 72 SPECint92, 59 SPECfp92 @ 100 MHz.

Suited for low-cost uniprocessor applications. SPARC v8 compliant. Performance is 1.59 SPECint95, 1.99 SPECfp95 @ 110 MHz without L2 cache.

Outdated Microprocessors

SPARC v8 compliant. Performance is 3.11 SPECint95, 3.10 SPECfp95 @ 75 MHz 1 MB L2 cache.

The SuperSPARC-I is the oldest member of the SuperSPARC family of microprocessor products. The SuperSPARC-I is a highly integrated, high performance superscalar microprocessor designed using a state-of-the-art BiCMOS process. The SuperSPARC-I is intended for use in a broad range of applications from uniprocessor desktop machines to large multiprocessor servers. SPARC v8 compliant. Performance is 1.13 SPECint95, 1.38 SPECfp95 @ 40 MHz without L2 cache.

Fujitsu SPARC Microprocessors

	What's new in Fujitsu	Microelectronics	Worldwide

The Fujitsu SPARC64-GP is superscalar, super-pipelined processor implementing the SPARC V9 architecture, designed and manufactured by Fujitsu.
Contains 17,600,000 transistors. The target operating frequencies are 225, 250, 272 and 296 MHz, performance is 19.2 SPECint95, 30.5 SPECfp95 @ 296MHz 8 MB L2 cache.

Targeted at network system applications, including hubs, routers and systems that support ATM technology; suitable for high-speed color laser printers.
The MB86860 features a superscalar RISC CPU core and 64-bit SDRAM interface, along with 16KB of each of instruction and data cache. The MB86860 series performs integer arithmetic operations compatible with conventional SPARC instructions. Its SPARClite buses are compatible with the other SPARClite family of devices. The target operating frequency is 200MHz.

Outdated Microprocessors

Designed to support low-cost uniprocessor systems, TurboSPARC is ideal for applications needing low-cost, single processor platforms like the SPARCstation 5. The target operating frequency is 170MHz, L2 cache -- 512KB, performance is 3.53 SPECint95, 3.00 SPECfp95.

Digital Alpha Microprocessors

	What's new in	Alpha Microprocessors	AlphaServer

Alpha 21464 (EV8) "Arana" 64-bit SMT microprocessor

Future Digital/Compaq's microprocessor, scheduled for production in 2003. It is expected to be fabricated in 0.125-micron SOI-compatible CMOS process with copper interconnects and low-k dielectrics. The 21464 should be available in 1.2GHz through 2GHz bins; at its 1.4GHz design center the microprocessor is expected to deliver ~140-200 SPECint95 and ~300-400 SPECfp95 of performance. Other 21464 characteristics are: transistor count - about 250 million, power dissipation - 150W, Vdd - ~1.2V. Alpha 21464 will implement Simultaneous MultiThreading (SMT) technique. The technique exploits thread-level parallelism to make better use of processor resources. Use of SMT will make EV8 microprocessor act like either a four-way SMP system or 8-wide issue superscalar depending on workload features. An information on the 21464 could be found in "Designers cut fresh paths to parallelism " by EE Times staff and in slide presentation at Microprocessor Forum '99 "Simultaneous Multithreading: Multiplying Alpha Performance"PostScript format by Joel Emer [ "Simultaneous Multithreading: Multiplying Alpha Performance" Microsoft PPT format]

Alpha 21364 (EV7) .18 micron 64-bit RISC microprocessor

Forthcoming Digital/Compaq's microprocessor. Shipments of 21364-based system are expected to begin in early 2001. Performance will be 70 SPECint95 and 120 SPECfp95 at speeds above 1 GHz. The 21364 is scheduled to debut at 750MHz and will eventually push to 1.2GHz. It will also include an integrated memory controller and a faster, next-generation EV7 bus. It will be designed for use in symmetric-multiprocessing implementations, where up to 64 processors can be ganged in a single server. On-chip transistor count will jump to the 100 million range. The new Alpha will also implement some of the same advanced code-optimization techniques Intel Merced is eyeing. The major difference between Merced and Alpha 21364 in this respect is static vs. dynamic. That is, Merced is doing everything as statically as it possibly can, the 21364 is doing everything as dynamically as it possibly can. 21364 (EV7) will be followed by 21364A (EV78) processor - the same design, re-implemented in 0.125 micron IC process An information on the 21364 could be found in slide presentation at Microprocessor Forum '98 "Alpha 21364: A Scalable Single-chip SMP" by Peter Bannon, Compaq and in articles "Intel, Compaq gird for 64-bit battle" by Alexander Wolfe, EE Times, and "Battle lines drawn for next-generation MPUs" by EE Times staff.

The 21264B is a re-implementation of 21264A (EV67) microprocessor in 0.18 micron IC process. Frequency range is from 833 through 1250MHz. Performance results are 544 SPECint2000 and 658 SPECfp2000 at 833 MHz, with 8MB L2 cache
Currently it is in sample production. It is expected to ship in systems by the end of 2000.

The 21264A is re-implementation of 21264 (EV6) microprocessor in 0.25 micron IC process. Clock frequencies are 600, 667, 700, 731, 750 and 833MHz. Performance results are 533 SPECint2000 and 644 SPECfp2000 (50.0 SPECint95 and 100.0 SPECfp95) @ 833MHz.

The 21264 has 64KB L1 instruction cache and 64KB L1 data cache. Optional off-chip L2 cache is accessed over a 128-bit-wide backside bus. The 21264 instructions include specially developed Motion Video Instructions (MVI) to enhance visual computing and multimedia performance, enabing Alpha to compress DVD video using the MPEG2 video standard and Dolby AC3 audio standard in software and in full real-time.
The 21264 contains 15,200,000 transistors, die size is 16.7mm x 18.8mm = 314 mm² power dissipation is about 90 Watts at 575MHz. Clock frequencies are 466, 500, 525 and 575MHz. Performance results are 313 SPECint2K, 422 SPECfp2K (27.7 SPECint95, 58.7 SPECfp95) at 500 MHz with 4MB L2 cache
The best source of information on the 21264 features probably is an article "Alpha 21264 stakes off the claim - long before Merced" by Tom R. Halfhill, c't.
An information on Alpha 21264 could also be found in press release from Digital, in "The 21264..." Slide Presentation from Microprocessor Forum by Jim Keller, Digital, and in arcicle "Digital 21264 Sets New Standard..." by Linley Gwennap, MicroDesign Resources.

The target operating frequencies are up-to 612 MHz, performance is 18.8 SPECint95, 29.2 SPECfp95 @ 600 Mhz 8 MB L3 cache.
Additional information on Alpha 21164 could be found in the Digital Technical Journal, Volume 7, Number 1, Special Issue 1995.

The 21164PC is based on Digital 21164 Alpha microprocessor. It provides unparalleled performance of multi-media authoring, high-quality video conferencing, and 3D graphics. Unlike its competition, the 21164PC includes Digital Semiconductors MVI, enabling real-time video conferencing and MPEG II decode without additional hardware assistance.
The target operating frequencies are 400, 466, and 533 MHz, estimated performance is 14.3 SPECint95, 17.0 SPECfp95 @ 533 MHz.

Outdated Microprocessors

The 21066A is a highly integrated implementation of Digital's Alpha architecture for high-performance, PCI-based systems. Onchip functions include an industry-standard PCI I/O controller and a 21066A-exclusive graphics accelerator. The 21066A is offered with clock frequencies of 233 MHz and 100 MHz.

The target operating frequencies are 200, 233, 275, and 300 MHz.

The chip implements 64-bit architecture, designed to provide a huge linear address space and to be devoid of bottlenecks that would impede highly concurrent implementations.
An information on Alpha 21064 could be found in the Digital Technical Journal, Volume 4, Number 4, Special Issue 1992.

Hewlett-Packard Microprocessors

PA-8700 .18 micon 64-bit RISC microprocessor

Future HP microprocessor, expected to ship in servers and workstations in the first half of 2001. It was taped out in late March 2000. New HP processor keeps basic PA-8x00 architecture unchanged. The PA-8700 employs a .18 micron, silicon-on-insulator copper CMOS process, allowing for 2.25MB of on-chip cache (750KB I-cache + 1.5MB D-cache) -- the largest of any microprocessor and a 50 percent increase over the PA-8600. The PA-8700 contains 186 million transistors and occupies 16 x 19 mm = 304 mm2 of silicon. It is designed to operate at frequencies at and above 800MHz. For more information see press release HP Reveils PA-8700 Chip Details and HP white paper PA-RISC 8x00 Family of Microprocessors with Focus on PA-8700 (in PDF format).

PA-8600 is fabricated in the same IC process as previous PA-8500 microprocessor and it shows minor architecture changes from its predecessor. But re-implementation allowed for rising clock frequency up-to 552 MHz. PA-8600' performance results are 42.1 SPECint95, 64.0 SPECfp95 at 552MHz, without additional off-chip caches. Die size is 21.3 x 22 mm = 469 mm², transistor count is about 140 millon.
New performance features include new cache algorithms to enable faster access to data, and cache prefetch technology to load data from memory faster. High-availability features include error checking and correcting (ECC) on the 1.5MB of on-chip cache to improve real-time error correction. The PA-8600 will be enhanced further by the addition of lockstep capability, a technology that enhances high availability by enabling systems to compare processing steps and recover if errors are detected.
For more information see press release HP Unveils PA-8600 Chip Details

Incorporates 1.5 MB (512KB I-cache + 1MB D-cache) of L1 cache memory on the chip. Contains 140,000,000 transistors and occupies 469 mm² of silicon. The target operating frequencies are 360, 400 and 440MHz, performance is 31.8 SPECint95, 52.4 SPECfp95 @ 400Mhz, without additional caches.

The target operating frequencies are 200 and 236 MHz, performance is 17.4 SPECint95, 26.3 SPECfp95 @ 236Mhz 4MB external cache.
An information on the PA-8200 could also be found in HP Journal article "Four-Way Superscalar PA-RISC Processors".

The PA-8000 is the first processor to implement the complete PA-RISC 64-bit architecture. "Intelligent execution" is a concept denoting synergistic operation of all critical elements of the PA-8000. The set of functional units contains 10 instruction-execution units. The target operating frequencies are 160 and 180 MHz, performance is 12.3 SPECint95, 20.2 SPECfp95 @ 180 MHz.
An information on the PA-8000 could also be found in HP Journal article "Four-Way Superscalar PA-RISC Processors".

Several years ago it was determined that HP could best meet the needs of higher volume, more cost sensitive products by developing a set of CPUs tuned to the special requirements of these systems...
An information on the PA-7300LC could also be found in HP Journal article "The PA 7300LC Microprocessor: A Highly Integrated System on a Chip".

Outdated Microprocessors

SGI MIPS Products

	What's new in	MIPS	SGI Corporate

MIPS R14000 64-bit RISC microprocessor

It is expected to be released in early 2001. Target frequency is 500 MHz In 1998 SGI, battling recent losses, was embarking on a transition away from its MIPS Rx000-series. Nevertheless, John Mashey, SGI chief scientist, said, “SGI’s path extends IRIX/MIPS for an appropriately long time. IRIX has many great strengths and features for certain kinds of applications, and SGI will enhance and sustain it for a long time to come. I expect we’ll be selling IRIX/MIPS machines through 2006, at least, and supporting them for years longer. I expect there will still be IRIX/MIPS machines running a decade from now.” SGI has committed to at least three more CPUs beyond R14000. R14000A is a remapping of R14000 into a new technology. R16000 adds large on-chip L2 cache and L3 cache tags which improve cache-hit and cache-miss latencies. R18000 adds a second load/store unit and a second floating-point unit to achieve 4 FLOPS/clock, or 3.2 GFLOPS peak. Several designs are being considered for chips beyond R18000. For more information about MIPS Rx000 roadmap see The SGI IRIX/MIPS Roadmap

R12000A CPU was released in July 2000. It is a remapping of R12000 in NEC's 0.18 micron process technology. In addition, the new chip has better system bus running at 200 MHz - twice as much R12000' bus.
Operating frequencies are 360 and 400MHz, performance is 353 SPECint2000 and 407 SPECfp2000 (24.2 SPECint95 and 43.5 SPECfp95) @ 400 MHz, 8MB L2 cache.

Contains 6,900,000 transistors. Operating frequencies are 270 and 300MHz, performance is 264 SPECint2000 and 283 SPECfp2000 (17.3 SPECint95 and 27.5 SPECfp.) @ 300 MHz.

Has improved multiprocessor support. Was designed for digital media and network applications. Operating frequencies are 200 and 250 MHz, peak performance is 14.7 SPECint95, 24.5 SPECfp95 @ 250 MHz 4 MB L2 cache.

MIPS R8000/8010 (TFP) RISC microprocessors

Specialized, supercomputing microprocessors.

MIPS R5000 64-bit RISC microprocessor

Mid-range microprocessor.

MIPS R4600/4700 RISC microprocessor

Designed for desktop uniprocessor workstations.

MIPS R4000/4400 RISC microprocessor

Mid-range, computing workhorse microprocessors.

MIPS R4300i RISC microprocessor

The MIPS R4300i is a high-performance, low-cost microprocessor designed to power interactive consumer devices: interactive game consoles and set-top terminals.

MIPS R3000 32-bit embedded RISC microprocessor

The R3000 is the second-generation MIPS RISC microprocessor and follow up to the R2000A, the first commercially available RISC processor introduced in 1985.

NEC MIPS Microprocessors

	What's new in	NEC	Corporate

Suited for supercomputers, top-end Unix workstations and servers, systems targeting multimedia applications, and Internet servers.
Features 5 parallel 64-bit functional units, including 2 integer and 2 floating-point execution units; supports 512K - 16MB L2 cache; special multiprocessor functions for multiprocessor operation. Contains 7,150,000 transistors. The target operating frequency is 300 MHz, performance is 16.8 SPECint95, 27.8 SPECfp95 @ 300 MHz. Power demand is 27 Watts @ 300MHz.

Suited for high-end personal computers, workstations, multiprocessor systems and fault-tolerant systems. The target operating frequency is 200 MHz, performance is 9.0 SPECint95, 19.0 SPECfp95 @ 200 MHz.
An information on VR10000 could be found in press release from NEC.

The NEC VR5400 family, whose members are the VR5464 and the VR5432, is the best suited to high-end office automation and network communication applications. The target operating frequencies are 167 (VR5432), 200 and 250 (VR5464) MHz, performance is 10 SPECint95, 5.5 SPECfp95 @ 250 MHz. Maximum power demand is 4.4 Watts at 250 MHz.
An information on VR5400 could be found in press release from NEC.

Suited for high-performance embedded, multimedia and image processing systems. The target operating frequencies are 150, 180 and 200 MHz, performance is 5.5 SPECint95, 5.5 SPECfp95 @ 200 MHz.

Quantum Effect Design Microprocessor Family

	What's new in	QED

Suited for high-performance embedded applications such as network routers/switches, printers, games systems, low-end workstations, 3-D accelerators, and industrial control/vision systems. The RM7000 is available now with volume production scheduled for late Q3-98. The product is priced at $150 for 10,000-unit quantities.
The RM7000 implements the MIPS IV instruction set architecture and features integrated on-chip 256KB 4-way set associative, non-blocking L2 cache. The target operating frequency is 300 MHz, estimated performance is 12-14 SPECint95, 14-16 SPECfp95.

IBM Microelectronics Product Guide

	What's new in	IBM Microelectronics	PowerPC	S/390	RS/6000

The IBM POWER Microprocessors

POWER4 "Gigaprocessor" copper SOI 64-bit CMP microprocessor

IBM is developing a processor it hopes will fend off the IA-64 juggernaut. Speaking at Microprocessor Forum '99, chief-architect Jim Kahle described IBM's monster 170-million-transistor Power4 chip, which boasts two 1-GHz five-issue superscalar cores, a triple-level cache hierarchy, a 10-Gbyte/s main-memory interface, and a 45-Gbyte/s multiprocessor interface. Kahle said that IBM will see first silicon on Power4 in 1Q00, and systems would begin shipping in 2H01. For more information, read "Power4 Focuses on Memory Bandwidth" article by Keith Diefendorff

POWER3-II is a re-implementation of POWER3 in the copper 0.2 micron technology process. Operating frequncies are 333, 375, 400 and 450MHz. The performance is 316 SPECint2000 and 409 SPECfp2000 at 450 MHz (24.4 SPECint95 and 50.9 SPECfp95 at 375 MHz).

POWER3 family is developed for UNIX workstations, servers and supercomputers. The POWER3 is built specifically for the demanding graphic, analysis and simulation programs used by aerospace, automobile and drug manufacturers.
The new POWER3 is the first unified POWER/PowerPC chip. Here IBM's POWER series is merging with the PowerPC and phasing out as a distinct architecture. The chip features eight execution units fed by a 6.4 gigabyte-per-second memory subsystem. The core includes two high-bandwidth buses: a 128-bit 6XX architecture bus to main memory and 256-bit bus to the L2 cache that runs at processor speed. The POWER3 also has on-chip 64KB data cache and a 32KB instruction cache. Operating frequencies are 200 and 222MHz.
Future versions of the POWER3 -- that have already sampled -- will be manufactured in .20 micron CMOS 7S process, that adopts copper wiring (planned for 1999), and silicon on insulator (SOI) technology (in 2000).
An information on POWER3 processor could be found in "POWER3: Next generation 64-bit PowerPC Processor Design" white paper by IBM.

An information on POWER2 could be found in "PowerPC and POWER2: Technical Aspects of the New IBM RS/6000" and "POWER2 Architecture Implementations" whitepapers and in Vol. 38, No. 5, 1994 issue of IBM Journal of R&D.

The IBM PowerPC Microprocessors

The RS64 III processor is the second in a line of microprocessors (internally code-named the "Star Series") designed and used to power AS/400 and RS/6000 servers. The first microprocessor in this line was code-named "NorthStar" and is known on the RS/6000 system as the RS64 II, and on the AS/400 as the A50. The RS64 III microprocessor, internally referred to by the code name "Pulsar", powers the newly available RS/6000 S80 server systems.
The "NorthStar" processor was used as a base for the design of the RS64 III. The operating frequency of the RS64 III processor was increased to 450 MHz over its predecessor's 262 MHz debut. The increase in frequency was accomplished by leveraging IBM's new copper technology (CMOS 7S) along with redesign of timing critical paths. The size of the L1 instruction and data caches were doubled to 128 KB each. Innovative custom circuit design techniques were used to maintain the one cycle load-to-use latency for the L1 data cache. The branch mispredict penalty relating to the L1 instruction cache was also kept at zero or one cycle. The RS64 II processor's off-chip L2 cache directory was integrated into the new RS64 III chip. A new IBM silicon technology with higher density used in conjunction with copper technology allowed these new functions to be added to the RS64 III processor chip while shrinking the die size from RS64 II's 162 mm² to RS64 III's 140 mm².
The next step in the roadmap is to map the RS64 III design into IBM's newest technology breakthrough called SOI (Silicon On Insulator) to create a microprocessor with a frequency in excess of 500 MHz . Laboratory hardware testing is currently underway for the first SOI-based systems. Plans exist for another "Star Series" microprocessor that uses a future IBM SOI technology with a target product frequency of over 600 MHz.
An information on RS64-III could be found in "5th Generation 64-bit PowerPC-Compatible Commercial Processor Design" by IBM staff.

The PowerPC RS64 and RS64-II are superscalar processors optimized for commercial workloads. Target environments are characterized by heavy demands on system memory, both in the form of very large working sets and latency-sensitive serial dependencies. The processors have separate 64 KB L1 caches for instructions and data and L2 cache controllers. The L2 caches run at full processor speed.
The RS64-II contains a dedicated 32 byte interface to a private 4-way set associative 8MB L2 cache. The processor target operating frequency is 262MHz. The RS64 contains 16 byte interface to 2-way set associative 4MB L2 cache. The processor target operating frequency is 125MHz.
The RS64 is also known as Apache. It is a predecessor to the RS64-II/POWER3. It has three names depending on which server line it was used in. The AS/400 servers called it A35 while RS/6000 servers called it the RS64. Apache was the code name used during development. This chip is the first 64-bit AIX-compliant microprocessor shipped by IBM.
The A25 a.k.a. Muskie was predecessor of A35 and was only used on PowerPC AS/400 systems. It was the first 64-bit SMP PowerPC microprocessor (although it only ran OS/400).
The A10 a.k.a. Cobra is the world's first 64-bit PowerPC microprocessor. Like the A25 it too only ran OS/400.
An information on the A35, A25 and A10 could be found in a book "Inside the AS/400. 2nd ed." by Frank G. Soltis; RS64/RS64-II -related information -- in white paper "The RS/6000 Enterprise Server Model S70" and in technical report "4th Generation 64-bit PowerPC-Compatible Commercial Processor Design" by IBM.

Suited for the notebook, mobile and power conscious desktop computing segments. Supports 256KB, 512KB and 1MB off-chip L2 cache, operating at a half of processor frequency. The target operating frequencies are 200, 233, 266, 275, 300, 333, 350, 366 and 400 MHz, estimated performance is 18.8 SPECint95, 12.2 SPECfp95 @ 400MHz 1MB L2 cache. Contains 6,350,000 transistors. Typical power demand is 4.1 Watts @ 400MHz.
See also Motorola PowerPC 750 section.

Suited for the workstation, PC server and power user desktop segments. The target operating frequencies are 166-375 MHz, estimated performance is 15.6 SPECint95, 9.7 SPECfp95 @ 375 MHz 1 MB L2 cache. Contains 5,100,000 transistors. Power demand is 7.5 Watts @ 333MHz.

The target operating frequencies are 120-180 MHz, estimated performance is 6.2 SPECint95, 5.3 SPECfp95 on 180 MHz.

The PPC603e is low-cost, low-power 32-bit implementation of PowerPC architecture. The target operating frequencies are 200-300 MHz, estimated performance is 7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz. Contains 2,600,000 transistors. Typical power demand is 3.5 Watts, support special low power modes.

Optimized for embedded applications. The EM603e is based on PPC603e microprocessor and the key differences are it has no floating-point unit function and its cost (starts at less than $21) is substantially reduced by using plastic packaging and established, high-volume manufacturing processes. The target operating frequencies are 100, 166 and 200 MHz, estimated performance is 5.1 SPECint95 @ 200 MHz. Typical power demand is 5.1 Watts @ 200 MHz.

Suited for the notebook and power energy sensitive desktop computing segments. The target operating frequencies are 66, 80 and 100 MHz, estimated performance is 120 SPECint92, 105 SPECfp92 @ 100 MHz. Contains 2,600,000 transistors. Typical power demand is 3.0 Watts. Additional information could also be found at white paper "PowerPC 603 Microprocessor" by IBM.

Suited for advanced home entertainment and educational devices with audio/video, multimedia, and complex graphics requirements. The target operating frequencies are 66 and 80 MHz, estimated performance is 48 SPECint92 @ 80 MHz. Contains 1,000,000 transistors. Power demand is less than 1.2 Watts @ 66 MHz, support special low power modes.

The PowerPC 601 microprocessor is a superscalar design capable of issuing and retiring three instructions per clock. Instructions issue to multiple execution units, execute in parallel, and can complete out of order, while preserving program correctness. It integrates three execution units - an integer unit, a branch processing unit, and a floating-point unit.

Outdated Microprocessors

The chip supported x86 architecture, 32-bit and 64-bit PowerPC architecture. A mode switch from PowerPC to x86 or vice versa took five CPU clocks. While the first pass of hardware performed reasonably, pass two was killed and that level of silicon was never tested.
Additional information could be found in an article "Microsoft killed the PowerPC 615" by The Register.

IBM Microelectronics x86 Microprocessor Products

The IBM x86 microprocessors are Cyrix designed, IBM manufactured processors.
National announced it has reached agreement with IBM for termination of the existing wafer manufacturing and marketing agreement between National's Cyrix subsidiary and IBM. Under terms of the agreement IBM will cease the sale of Cyrix-designed processors before the end of calendar 1998, and Cyrix subsidiary will be relieved of its wafer purchase obligation to IBM.

An information on PR performance levels.
Release 1.0 of the PR specification was created by several companies including AMD, Cyrix, IBM Microelectronics, and SGS-Thomson. Processors designated PR266 and below were rated according to release 1.0, while processors designated PR300 and above will be rated according to release 2.0 of the PR specification, which was created by IBM Microelectronics.

Pentium II-class microprocessor. The IBM 6x86MX PR300 uses the same design as the Cyrix M II-300. IBM 6x86MX operates at performance levels up-to PR333.

Pentium-class microprocessor. Operates at performance levels PR150, PR166 and PR200.
6x86L is low-power version of the 6x86 microprocessor.

5x86C 32-bit CISC microprocessor

486DX4-class microprocessor.

Motorola PowerPC Chips

	What's new in	Semiconductors	PowerPC products

PowerPC G4 copper .2 micron 32-bit microprocessor

Future Motorola chip, aimed at the embedded market as well as the PC (including Apple Mac). Should go into production by the middle of 1999. The G4 is the first PowerPC to feature Motorola's AltiVec graphic vector processing operations. Supports 512K to 2MB of backside L2 cache, connected via 64-bit or 128-bit buses. Multiple G4s can access each other's caches, offering much improved multi-processing performance. Will offer 10-15 times the performance of the current PowerPC 750. Contains 10,500,000 transistors, consumes less than 8 Watts @ 400 MHz. An information on the G4 could be found in articles "Motorola launches PowerPC G4" and "Second-stage PowerPC G4 details emerge" by Tony Smith, The Register.

An information on AltiVec technology could also be found in press release "Motorola's New AltiVec Technology To Expand Industry Definition of Microprocessors" from Motorola.

The PowerPC 620 microprocessor features a high bandwidth memory subsystem ideal for symmetric multiprocessing, transaction processing and numerically intensive computing. It is a superscalar design capable of issuing four instructions per clock cycle to six independent execution units. The PowerPC 620 microprocessor supports out-of-order execution with in-order instruction completion. L2 cache could be 1MB to 128MB in size. The target operating frequencies are 133, 180 and 200 MHz, estimated performance 8.0 SPECint95 and 10.0 SPECfp95 @ 200 MHz 4 MB L2 cache. Contains 7,000,000 transistors. Power demand is 40 Watts @ 200 MHz.
An informtion on 133 MHz PowerPC 620 could also be found at IBM "PowerPC 620 RISC Microprocessor" document.

Suited for the notebook, mobile and power conscious desktop computing segments. Supports 256KB, 512KB and 1MB off-chip L2 cache, operating at a half of processor frequency. The target operating frequencies are 200, 233, 266, 300, 333 and 366 MHz, estimated performance is 16.1 SPECint95, 9.9 SPECfp95 @ 366MHz 1MB L2 cache. Contains 6,500,000 transistors. Typical power demand is 5.0 Watts @ 366MHz.
See also IBM PowerPC 750 section.

Suited for high-end communications and networking applications such as hubs, routers and LAN switches, network computers and storage controllers. Does not support additional L2 cache. The target operating frequencies are 200, 233, 266 and 300 MHz, estimated performance is 12.2 SPECint95, 7.1 SPECfp95 @ 300MHz. Contains 6,500,000 transistors. Power demand is 3.4 Watts @ 300MHz.
See also PowerPC 740 information at IBM.

Optimized for embedded applications. EC603e microprocessors are pin and software compatible with PowerPC 603e, PowerPC 604e, and PowerPC 740 microprocessors with the exception of floating point support. The target operating frequencies are 100, 133, 166, 200, 233, 266 and 300 MHz, estimated performance 7.4 SPECint95 @ 300 MHz. Typical power demand is 4 Watts @ 300 MHz.

Intel Developers

	What's new in	Intel	Intel processors

Covers Intel microprocessors from 4004 to the most recently designed.

Answers some questions on Intel current and forthcoming microproprocessors.

	McKinley copper .18 micron 64-bit microprocessor
	Future Intel chip. Should be sampled in 2001. An information on the McKinley could be found in articles "What's Wrong With Merced" by Linley Gwennap, MicroDesign Resources and "Is Merced doomed?" by Michael Kanellos, CNET.

Itanium (Merced) .18 micron 64-bit EPIC/CISC microprocessor

The microprocessor has been in development since 1994. It was scheduled for production in mid-2000 but still it is in sampling Initial version of Merced will be used in high-end servers. It will include a choice of 2 Mbytes or 4 Mbytes of L2 cache and will sell for about $5,000. According to multiple sources, Merced will score about 40 to 50 SPECint95 and perhaps 75 SPECfp95 (See an article "Alpha 21264 stakes off the claim - long before Merced" by Tom R. Halfhill, c't.) A less powerful version of Merced will separate the secondary cache from the CPU and delivers the cached data at half the speed. Less powerful chip will sell for about $1,000. Its production is expected in 2001. The Merced will incorporate two separate cores: IA-64 and Pentium II, where the second one is targeted at support of x86 applications. These applications will feature just the performance of present-day Pentium II. The Merced is facing some problems for now. See references list for the McKinley processor. Additional information and list of references on the Merced could be found in article "Merced Facts and Speculations" by Alexei Pylkin, Supercomputer Software Department RAS.

Pentium-4 (Willamette) .18 micron 32-bit CISC microprocessor

The Pentium-4 was released for production on Nov 20, 2000. The Pentium-4 is fabricated in Intel's 0.18 micron CMOS process. Its die size is 217 mm2, power consumption is 50W. The Pentium 4 is available in 1.4GHz and 1.5Hz bins. At 1.5GHz the microprocessor delivers 535 SPECint2000 and 558 SPECfp2000 of performance. Pentium-4 is the first completely new x86-processor design from Intel since the Pentium PRO processor, with its P6 micro-architecture, was introduced in 1995. Pentium-4' micro-architecture is known as NetBurst. It has many interesting features. - Compared to the Intel Pentium-III processor, Intel's NetBurst micro-architecture doubles the pipeline depth to 20 stages. In addition to the L1 8 KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12 K decoded micro-ops in the order of program execution. The on-die 256KB L2-cache is non-blocking, 8-way set associative. It employs 256-bit interface that delivers data transfer rate of 48 GB/s at 1.5 GHz. The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register for data movement. Pentium-4' NetBurst micro-architecture introduces Internet Streaming SIMD Extensions 2 (SSE2). This extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. Pentium 4 processor's 400 MHz (100 MHz "quadpumped") system bus provides up to 3.2 GB/s of bandwidth. The bus is fed by dual PC800 Rambus channel. This compares to 1.06 GB/s delivered on the Pentium-III processor's 133-MHz system bus. Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in a half clock cycle. The integer register file runs also runs at the double frequency. For more information on the new Intel Pentium-4 processor see official Intek press-release Intel Introduces The Pentium 4 Processor and Intel Pentium-4 product brief. Also look at Pentium-4 processor home page

"Coppermine" is a 0.18 micron implementation of Pentium III processor. It adds 256KB unfied L2 cache on-chip.
Die size is 106 mm², operating frequencies are 500, 533, 550 600, 650, 667, 700, 733, 750, 800, 850, 866, 933 and 1000MHz. Performance results are 442 SPECint2000 and 335 SPECfp2000 (46.8 SPECint95 and 32.2 SPECfp95) at 1GHz. For more information, see Pentium III Product Overview from Intel

Pentium III implements basically the same architecture as Pentium II. It introduces two new features:
- Internet Streaming SIMD Extensions (SSE) - 70 new instructions for multimedia support
- Intel Processor Serial Number (PSN) - each Pentium III microprocessor is marked with its unique ID.
Operating frequencies are 450, 500, 533, 550 and 600MHz. Performance results are 24.6 SPECint95 and 16.2 SPECfp95 at 600MHz For more information, see Pentium III Product Overview from Intel

A version of the Pentium II microprocessor, targets high-end workstations and servers used in Internet services, corporate data warehousing, digital content creation, and electronic and mechanical design automation. Currently Xeon-based systems can be configured to scale up-to two processors. Intel announced that Pentium II Xeon processors for four-way servers will be available in early 1999.
The chip comes with 512KB, 1MB, or 2MB off-chip L2 cache, running at clock speed. Target operating frequencies are 400 and 450 MHz, performance is 17.4 SPECint95, 13.0 SPECfp95 @ 450MHz 512KB L2 cache.

The Pentium II integrates attributes of the Pentium Pro plus the capabilities of MMX technology. It is scalable up to two microprocessors in a multiprocessor system. Contains about 7,500,000 transistors. The Pentium II has 512 KByte off-chip L2 cache. Target operating frequencies are 233, 266, 300, 333, 350, 400 and 450 MHz, performance is 17.2 SPECint95, 12.9 SPECfp95 @ 450 MHz.

Targeted at mobile PCs market segment, mobile Pentium II has the same chip architecture and performance as Pentium II but low power consumption -- 9.0 Watts @ 300MHz. Target operating frequencies are 233, 266 and 300 MHz, estimated performance is 11.9 SPECint95, 8.8 SPECfp95 @ 300 MHz.

Targeted at sub-$1200 market segment. Contains 7,500,000 transistors. Has not L2 cache -- a so-called Covington design. Target operating frequencies are 266 and 300 MHz, performance is 7.73 SPECint95, 6.57 SPECfp95 @ 266MHz.
Intel also offer a version of the Celeron with 128KB on-chip L2 cache, developed under the code name Mendocino. Target operating frequencies are 300 (so-named "Celeron-300A") and 333 MHz. 366MHz Mendocino is scheduled for production in Q1-99.

Target operating frequencies are 150, 166, 180, and 200 MHz, on-chip L2 cache is 256KB, 512KB or 1 MB, performance is 8.58 SPECint95, 6.48 SPECfp95 @ 200 MHz 512 Kbytes L2 cache.
Intel created the ASCI Option Red Supercomputer (also known as the TFLOPS), based on the Pentium Pro processors. For more information see An Overview of the Intel TFLOPS Supercomputer in Intel Technology Journal.

Low power consumption version of the Pentium MMX processor targeted at low-cost mobile PCs and mini-notebooks markets. Target operating frequencies are up to 300MHz, power consumption is 6.1 Watts @ 300MHz

The Pentium processor with MMX technology runs existing software 10-20% faster than the original Pentium processor at the same clock speed. Target operating frequencies are 166, 200, and 233 MHz, estimated performance is 7.12 SPECint95, 5.21 SPECfp95 @ 233 MHz. Contains 4.5 million transistors.

Target operating frequencies are 60, 66, 75, 90, 100, 120, 133, 150, 166 and 200 MHz, estimated performance is 5.17 SPECint95, 4.32 SPECfp95 @ 200 MHz.
See also "The Pentium Processor Technical Backgrounder".

The same processor upgrades existing upgradable 150 and 180 MHz Pentium Pro-based systems to 300 MHz, and 166 and 200 MHz systems to 333 MHz and could support systems in single and dual processor configurations. Manufactured on the same processor core as the Pentium II Xeon processor. Has 512KB L2 cache with bus running at the full speed of the processor. Performance is 13.5 SPECint95, 7.98 SPECfp95 for 333 MHz option.

The member of the i960 processor family, the 80960RP, incorporates a complete PCI-based I/O subsystem including a DMA controller, memory controller, I2C interface, APIC interface, and a PCI-to-PCI bridge.

32-bit register-based architecture with 32 registers. Enhanced CISC-like instruction set optimized for embedded applications. Low cost: processors available from about $10.

Outdated Microprocessors

The i860 was used as the data processor in Intel's massively-parallel Touchstone and Paragon supercomputers.
Additional information on the i860 could be found in "i860 Microprocessor Architecture Overview" document by Chow Hon Soon.

Advanced Micro Devices PC Processors

	What's new in	AMD

Athlon (K7) .25 micron 32-bit CISC microprocessor

It is targeted at graphic intensive PCs in the $2,000-$3,000 bracket. The Athlon features a nine-issue superscalar microarchitecture, a superscalar pipelined floating point unit, 128KB of on-chip L1 cache, a module mechanically interchangeable with Intel's Slot 1 single-edge connector module, and a 200MHz Alpha EV6-compatible system bus interface with support for scalable multiprocessing. AMD claims the Athlon floating point unit as the most architecturally advanced floating point capability ever delivered in an x86 microprocessor. Clock frequencies are 500, 550, 600, 650 and 700MHz on 0.25-micron process technology AMD and Motorola also announced plans for collaborative development of future logic process technology platforms featuring copper interconnects, which enables to produce gigahertz Athlon microprocessors in the year 2000. Performance results are 31.7 SPECint95 and 24.0 SPECfp95 @ 700 MHz

K6-3 (Sharptooth) .25 micron 32-bit CISC microprocessor

The AMD K6-3 (old name is K6+ 3D, code-name Sharptooth) is forthcoming improved version of the AMD-K6-2 microprocessor with on-chip 256K L2 cache, which operates at processor frequency, and supporting an optional L3 cache. The K6-3 is scheduled for production in Q4-98 and its mobile versions are expected in Q1-99. The K6-3 will fit into the same Socket 7 architecture motherboards the older K6 and K6-2 chips use. Clock speeds will start at 450MHz. Contains 21,300,000 transistors.

The AMD K6-2 (old name is K6 3D) processor combines superscalar MMX capability and new 3DNow! proprietary instructions developed by AMD and targeted at graphic intensive applications and 3d games. The processor enables accelerated and enhanced graphics with full-featured MPEG-2 video and AC-3 sound. The K6-2 supports the 100MHz bus and the Accelerated Graphics Port (AGP) specifications.
Contains 9,300,000 transistors. Clock speeds are 266, 300, 333, 350, 366, 380 and 400 MHz. 450MHz version of the K6-2 is expected in 1Q-99. The 333MHz AMD-K6-2 has a peak floating point performance of 1.333 Gigaflops (compare with the 0.4 Gigaflops of a 400MHz Pentium II).

AMD K6 is superscalar microprocessor targeted at PC workstation segment. The K6 processor architecture is fully x86 binary code compatible and executes industry-standard MMX instructions. Contains 8,800,000 transistors. Target operating frequencies are up-to 300Mhz.
Mobile version of the K6 consumes typical 6.6 Watts @ 300Mhz.

Cyrix Product Info

	What's new in	Cyrix

An information on PR performance levels. See also IBM Processor Performance Rating Specification. Release 2.0

M3 (Jalapeno) .18 micron 32-bit CISC microprocessor

The Jalapeno is the first completely new architecture from Cyrix since the original 6x86 processor. Jalapeno includes an 11-stage deep-pipeline, a completely new floating point unit, a 3D graphics engine and numerous memory enhancements. The 256K on-chip L2 cache is 8-way associative, 8-way interleaved and fully pipelined to operate at the core frequency. The Jalapeno supports execution of both MMX and 3DNow! instructions. The M3 is expected to debut in the fourth quarter of 1999 in the 600 - 800MHz speed range. An information on M3 (Jalapeno) could be found in press release "Cyrix Unveils Jalapeno Core Architecture" from Cyrix.

	MXi 32-bit CISC microprocessor
	Future Cyrix microprocessor, an updated version of the MII with 3D graphics capabilities.

Improved version (greater operating frequencies, advanced manufacting process) of the Cyrix 6x86MX. Targeted at low-cost sub-$1200 computer market segment, the M II is the best suited for end-user multimedia applications. Delivers Winstone98 performance comparable to 300 and 333 MHz Pentium II (PR300, PR333).

Features MMX instructions, enhanced memory management unit, and 64 KB unified internal cache. Delivers Performance Rating up-to PR266.

Merges graphics, audio, memory control and the PCI interface into the CPU chip. Supports MMX feature. Target operating frequencies are up-to 266 MHz.

Outdated Microprocessors

SGS-Thomson STMicroelectronics

	What's new in	STMicroelectronics

The chip includes Pentium compatible processor, PCI, ISA, IDE, DMA, interrupt controllers, graphics subsystem and video pipeline. Target operating frequencies are up to 133 MHz.

Texas Instruments Digital Signal Processing

	What's new in	TI DSP Solutions

Multiprocessor DSPs with up to four 32-bit DSPs and a 32-bit RISC master processor - on a single piece of silicon delivering up to 2 BOPS. The processing power of the 'C8x devices supports any application that requires high-performance digital signal processing.

The TMS320C67x adds floating point capability (including hardware-supported 64-bit double precision operations) to six of the eight functional units available on the TMS320C62x processors and, therefore, the 'C67x instruction set is a superset of the 'C62x fixed point instructions. Target operating frequency is 167 MHz, performance is up to 1 GFLOPS on single precision and 420 MFLOPS on double precision operations. Sampling of the 'C6701 (the first chip in TMS320C67x family) is planned for the second half of 1998.

TMS320C62x family includes single chip: 'C6201. The 'C6201 contains 270,000 transisters, has 1 Mbit on-chip RAM, and executes up to eight instructions every clock cycle. Target operating frequency is 200 MHz, peformance is up to 1600 MIPS.

The TMS320C5x generation of digital signal processors from Texas Instruments, with its unparalleled combination of performance, affordability, integrated memory choices and power-management features, has become the new 16-bit DSP standard...

The TMS320C4x devices are optimized for parallel processing. The 'C4x family combines a high-performance CPU and DMA controller with up to six communication ports to meet the needs of multiprocessor and I/O-intensive applications.

The TMS320C3x generation is the first of TI's 32-bit floating-point digital signal processors. The 'C3x devices provide an easy-to-use, high-performance architecture, which allows users to develop breakthrough products quickly.

'C27x combines the high-speed multiply-and-accumulate operations of DSPs with the intensive input/output operations characteristic of MCUs. It has been optimized for high-performance, real-time embedded control applications. 'C27x delivers 100 MIPS performance.

Hitachi SuperH Family

Hitachi microprocessor, targered at multimedia products such as set-top boxes and car navigation systems. The SH7750 features 8 Kbytes instruction and 16 Kbytes data L1 caches, typical power dissipation is 1.5 Watt. Target operating frequencies are 167 and 200 MHz, peformance is 360 Dhrystone MIPS, peak 1.4 GFLOPS @ 200 MHz.

Other Sources of Information

PowerPC FAQ by Derek Noonburg

This FAQ was posted on comp.sys.powerpc, comp.answers, and news.answers newsgroups.

"CHIPLIST" by Aad Offerman

Mostly of x86 architecture.

This survey is a part of "Computer Organization and Design: The Hardware/Software Interface, Second Edition" book, by David A. Patterson and John L. Hennessy. The survey includes technical information on Alpha, PA-RISC, PowerPC, MIPS and SPARC as well as some embedded RISC processors.

You could use it as glossary of microprocessor terms.

EG³ Electronic Engineers' Toolbox

EG3 indexes Internet information specific to DSP, embedded systems, Internet-enabling, board-level, MCU's/MPU's, real-time computing, and software development for electronic design.

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Currently VLSI Microprocessors web-site is maintained by Alexei S. Pylkin, M.Sc. in CS,
Lead Engineer for ICMMG (former Computing Center) of Russian Academy of Sciences,
Academgorodok, Novosibirsk, Russia

Alexei Pylkin could be accessed at e-mail pylkin@ssd.sscc.ru

The site was initially developed and maintained by Oleg Yu. Repin, M.Sc. in Mathematics,
Leading Programmer-Researcher for the Supercomputer Software Department,
Russian Academy of Sciences,
ICMMG (former Computing Center), Academgorodok, Novosibirsk, Russia